http://dspace.daffodilvarsity.edu.bd:8080/handle/123456789/2035 2026-04-05T17:28:33Z 2026-04-05T17:28:33Z Dignum, Virginia http://dspace.daffodilvarsity.edu.bd:8080/handle/123456789/2181 2019-06-22T07:17:47Z 2017-09-25T00:00:00Z

Responsible Artificial Intelligence: Designing Ai for Human Values Dignum, Virginia Artificial intelligence (AI) is increasingly affecting our lives in smaller or greater ways. In order to ensure that systems will uphold human values, design methods are needed that incorporate ethical principles and address societal concerns. In this paper, we explore the impact of AI in the case of the expected effects on the European labor market, and propose the accountability, responsibility and transparency (ART) design principles for the development of AI systems that are sensitive to human values.

2017-09-25T00:00:00Z Wang, Yu Liang, Shuang Yao, Song Shan, Yi Han, Song Peng, Jinzhang Luo, Hong http://dspace.daffodilvarsity.edu.bd:8080/handle/123456789/2153 2019-06-22T07:18:38Z 2017-09-25T00:00:00Z

Reconfigurable Processor for Deep Learning in Autonomous Vehicles Wang, Yu; Liang, Shuang; Yao, Song; Shan, Yi; Han, Song; Peng, Jinzhang; Luo, Hong The rapid growth of civilian vehicles has stimulated the development of advanced driver assistance systems (ADASs) to be equipped in-car. Real-time autonomous vision (RTAV) is an essential part of the overall system, and the emergence of deep learning methods has greatly improved the system quality, which also requires the processor to offer a computing speed of tera operations per second (TOPS) and a power consumption of no more than 30 W with programmability. This article gives an overview of the trends of RTAV algorithms and different hardware solutions, and proposes a development route for the reconfigurable RTAV accelerator. We propose our field programmable gate array (FPGA) based system Aristotle, together with an all-stack software-hardware co design workflow including compression, compilation, and customized hardware architecture. Evaluation shows that our FPGA system can realize real-time processing on modern RTAV algorithms with a higher efficiency than peer CPU and GPU platforms. Our outlook based on the ASIC-based system design and the ongoing implementation of next generation memory would target a 100 TOPS performance with around 20 W power.

2017-09-25T00:00:00Z