Analysis Of High-K And Metal Gate Influence On The Electricalbehavior Of 14 Nm Double-Gate Nmos Fets

Abstract

With the continuous downscaling of metal oxide semiconductor field effect transistors (MOSFETs), the performance and scaling limitations have driven emerging innovative device architectures. In this work, we perform a comprehensive simulation-based study of NMOS design and analysis at 14 nm with the test-based simulator, Silvaco TCAD. Our device has a novel “sandwich dielectric” design intended for optimal threshold voltage (Vth) and I-V characteristics (Id-Vd). It is suggested that better electrostatic control can be achieved by using a "sandwich" structure made up of a 0.1 nm zirconium dioxide (ZrO₂) interface layer, a 0.1 nm hafnium dioxide (HfO₂) dielectric layer and a 0.1 nm silicon nitride (Si₃N₄) barrier layer. The gate electrode is tantalum nitride (TaN) with a work function of 4.3 eV, and the source and drain electrodes are aluminum (Al) with a work function of 4.1 eV. Combining these materials with the defined structural arrangement gives better gate control, fewer short-channel effects, and better charge carrier mobility. Finally, our simulation results suggest that our device has considerably enhanced electrical performance. In the form of drain current versus drain voltage (Id-Vd) characteristics, better control of voltage (Vth) and drive currents (Id-Vd) give higher drive currents, lower leakage current, and better switching performance. To address these challenges, we propose a double-gate 14 nm NMOS, a promising device for next-generation low-power, high-power electronic devices. This work contributes critically to the field of nanoelectronics with a detailed study of material selection, structural innovation, and its impact on device performance. Future research on advanced MOSFET architectures and transistor technologies beyond 14 nm can benefit from this study's insights.