DEGIEN AND IMPLEMENTATION OF DIGITAL POWER FACTOR METER

Abstract

This paper identifies with the field of building up an electronics Digital power-factor (PF) meter to supplant the ordinary electrodynamic type. The plan depends on voltage to recurrence change and twofold rate increase methods. For the primary half estimating period, a flag relative to the pinnacle voltage Vm is connected to control the exchanging limit dimension of the comparator of the voltage to recurrence converter (VFC), while the contribution of the VFC is kept at reasonable steady dimension, hence delivering a yield recurrence conversely corresponding to Vm, which is considered and connected an information to a parallel rate multiplier (BRM). For the second half estimating period, a flag corresponding to the result of the pinnacle voltage and the power factor Vm cos(ϕ), is connected to the VFC, while the starting dimension of the comparator is kept consistent. The VFC recurrence yield is then specifically relative to Vm cos(ϕ). This is made accessible through gating system to the BRM recurrence input. The BRM recurrence yield is summed over a predetermined timeframe to give PF data.