Design and Investigation of a New Protocol for a Single Wire Low Speed Bi-Directional Data Bus for Embedded Systems

Abstract

A new protocol for a low speed single wire half duplex serial digital data BUS utilizing MasterSlave configuration is proposed in this thesis. Industry standard single wire data BUS already exists in the market from multiple large name brands. These existing single wire protocols work by either using delay based digital logic state definition or Manchester encoding or some other encoding technique to multiplex both data and clock in the same transmitted bit. Existing data buses generally have a standard speed of around 15Kbps and around 100kbps at high speed or overdrive mode. The data is kept synchronous by syncing with falling or rising edge of the transmitted signal. The proposed data BUS tries to multiplex data and clock in an unconventional way. An existing standard for digital logic state definition has been slightly modified to suit the requirements. In the research, attempts are made to combine both a digital data and an analog Clock signal on the transmitter side and separate the clock and digital data on the receiver side. The hardware for the combining and separating signals are designed to be as simple as possible. The whole system is tested out on a breadboard prototype using off the shelf components. Prototype consists of the individual transmitting and receiving modules and their respective Microcontroller Unit(s) running respective behavior model programs to simulate a functional transmitter and receiver, that are communicating predefined data at real time. Prior to construction of the prototype, detailed computer simulation has been generated to observe to viability of the idea, to test the designed circuits and to find and fix the bugs and signal glitches. Computer simulation is kept limited between voltage sweep and interactive simulation depending on the circuit and the virtual test instruments made available by the said simulator. Although signal degradation occurred in the prototype, which was not present in the computer simulation, the BUS behaved exactly as predicted. Results from both the simulations and hardware prototype shows that it is possible to communicate in the proposed manner. The result from the proposed Single Wire data BUS is compared to the existing protocols to reveal that it is possible to theoretically exceed (21Kbps to 27Kbps) the standard speed of the existing protocols even with the breadboard implementation of the proposed data BUS.