Algorithms for synthesis and average distribution of variable sized MOS components for efficient Analog VLSI devices

dc.contributor.author	Faisal Al Ameen, Mahmudul
dc.contributor.author	Islam, Md. Didar
dc.contributor.author	Hossain, Syed Akhter
dc.date.accessioned	2018-09-27T06:12:46Z
dc.date.accessioned	2019-05-27T09:59:30Z
dc.date.available	2018-09-27T06:12:46Z
dc.date.available	2019-05-27T09:59:30Z
dc.date.issued	2008-07-25
dc.identifier.uri	http://hdl.handle.net/20.500.11948/3327
dc.description.abstract	In the field of Analog VLSI layout design, large variation of MOS component sizes causes mismatches and reduces the performance and splitting is necessary to reduce the variation. On the other hand, intensity of imposing always varies during fabrication. In this ongoing research, the solutions of above problems are introduced with some algorithm implementations. Two different sizes of components can be split into optimized number of pieces and an algorithm distributes them in an average and symmetrical (better) arrangement such that it can ensure average imposing and the efficiency increases. The computer generated solutions are compared with other possible solutions and proved better. Full Text Link: http://doi.org/10.1109/ICCITECHN.2007.4579437	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE Xplore	en_US
dc.subject	integrated circuit layout	en_US
dc.subject	MOS analogue integrated circuits	en_US
dc.subject	MOS components	en_US
dc.subject	analog VLSI devices	en_US
dc.title	Algorithms for synthesis and average distribution of variable sized MOS components for efficient Analog VLSI devices	en_US
dc.type	Article	en_US